As device density continues to increase in integrated circuits, line widths and line separation distances must become smaller. As a result, detrimental capacitive effects may be experienced in metal lines connecting transistors on a substrate. The capacitive effects can result in two ways. First, two adjacent metal lines on a single metalization layer may be sufficiently close that they, together with the dielectric separating them, act as a capacitor. Second, metal lines on two adjacent metalization layers that are lined substantially on a common vertical axis can, together with the dielectric separating them, act as a capacitor. In either case, when a change in potential is applied to a line with the goal of conducting current across that line, the applied change in voltage is resisted by the presence of adjacent metal lines which act as plates of a capacitor. Further, signals on adjacent lines may interfere with one another resulting in xe2x80x9ccrosstalk.xe2x80x9d
These phenomena can be understood with reference to FIG. 1. As shown, a typical integrated circuit cross-section 8 includes a semiconductor substrate 10 on which polysilicon gates 12 and field oxide 14 are formed. An interlayer dielectric 16 (or xe2x80x9cILDxe2x80x9d) entirely covers the field oxide, the gate electrodes, and the substrate. Commonly, the interlayer dielectric 16 is made from a phosphosilicate glass. A first metalization layer 18 is provided on top of ILD 16 and patterned to form metal lines as shown. Note that vias (openings) are formed through ILD 16 and include metal contacts 27 connecting polysilicon gate electrodes 12 to the metal lines of metalization layer 18.
After layer 18 has been patterned, an intermetal dielectric 20 (or xe2x80x9cIMDxe2x80x9d) is formed on top of metalization lines 18 and insulates those lines from a second metalization layer 22 which is also patterned to form separate metal lines. Interconnects 28 through IMD 20 connect the lines of first metalization layer 18 to the lines of second metalization layer 22. To insulate the conductive lines of the second metalization layer, a second intermetal dielectric layer 26 is formed on top of second metalization layer 22.
As shown with reference to first metalization layer 18 and second metalization layer 22, the individual metal lines of that metal layer may be disposed relatively close to one another. In one typical process, the height of the metal lines is about 0.7 micrometers and the width of such metal lines is about 0.4 micrometers. In addition, the individual lines may be separated by as little as 0.4 micrometers. When this is the case, the capacitive coupling between adjacent lines becomes quite pronounced.
In a technology having the line dimensions and separations indicated above, transistor switching speed may become limited by the metal lines. In this example, transistors connected by lines of greater than about 300 micrometers in length will begin to have their switching speed limited by the metal lines. For shorter line lengths, the switching speed is limited by the individual transistors. For longer line lengths, the switching speed is definitely limited by the capacitive effects experienced in the lines.
In many designs at least some of the transistors are separated by lines of at least 300 micrometers in length. Therefore, the capacitive coupling between adjacent lines represents a source of performance degradation. With this in mind, IC designers have investigated various approaches to reducing the capacitive coupling between adjacent lines and metalization layers. Of particular interest are those efforts which have strived to reduce the dielectric constant of the insulator material provided between adjacent metalization layers. A material""s dielectric constant is a measure of its ability to store electrical energy. The lower its dielectric constant, the less the material can behave as if it were a capacitor. And the less charge that it stores, the less any signals passing along adjacent conductive lines will be garbled or delayed by electrical interference.
One approach to reducing dielectric constant has involved the introduction of fluorine or fluoride species into silicon dioxide IMDs. This approach has been found largely unsatisfactory because free fluorine radicals and/or ions generated during the IMD deposition process can be particularly chemically aggressive and therefore hard to control. Other approaches to reducing the dielectric constant have involved replacing the silicon dioxide conventionally employed in IMDs with an organic polymeric material. These materials may have dielectric constants as low as about 2.0; silicon dioxide based materials in conventional IMDs have dielectric constants of about 3.9. Unfortunately, it can be quite difficult to find polymeric materials which have a thermal stability adequate to withstand high temperature deposition and annealing process steps.
Commonly, during metal deposition steps, the wafer under process is exposed to temperatures of over 350xc2x0 centigrade. Thus, alternative IMD materials must be able to withstand temperatures in the neighborhood of at least 350-450xc2x0 centigrade. Unfortunately, suitable polymers rarely can withstand such temperatures. If the polymers are cross-linked, they typically decompose at temperatures above 350xc2x0 centigrade. A material that loses more than 0.1% of its mass on exposure to a 450xc2x0 centigrade environment for 1 hour is unsuitable as an IMD dielectric. The lost polymer forms volatile materials which interfere with other process steps and create unacceptably high concentrations of dangling bonds. Thermoplastic polymers (which are not cross-linked) may also decompose at high temperatures. In addition, they may liquefy and simply flow off of the wafer. Obviously, such materials are unsuitable for use in integrated circuit fabrication.
Despite these problems, ongoing research efforts have identified certain thermally stable polymers which show substantial promise as low dielectric constant IMD materials. Often, such materials are at least slightly cross-linked and/or have a fairly rigid polymer backbone. For example, these materials may include ring structures such as phenyl groups or cyclic imide groups. Of particular note, many of the most promising polymeric IMD materials are fluorinated polymers. Thus, some promising materials include polycyclic backbones having substantial fluorine substitution. One material receiving much attention is polyfluoropyreline. This material is sufficiently stable at 450xc2x0 centigrade that it may be employed in conventional integrated circuit fabrication processes.
Unfortunately, it has been observed that polyfluoropyreline and related thermally stable fluorinated polymers do not adhere well to adjacent metalization lines. This is not surprising as fluorinated polymers are widely known to have very poor adhesive properties due to their low surface energies. Obviously, until these adhesion problems are overcome, thermally stable fluorinated polymers will not realize their potential as commercially viable IMD materials.
The present invention provides thermally stable polymeric IMDs and ILDs having enhanced adhesiveness by introduction of an adhesive material in the IMD or ILD polymeric material. In the preferred embodiments, the adhesive material resides only at the interface of the IMD or ILD with adjacent metalization or polysilicon layers.
One aspect of the invention generally provides an electronic circuit having a dielectric material for electrically isolating one or more conductive pathways. Specifically, the dielectric material includes a thermally stable polymeric material having its adhesiveness to the one or more conductive pathways improved by a polar material disposed on at least an interface between the polymeric material and the one or more conductive pathways. When the electronic circuit is an integrated circuit, at least three options for using the invention are available: (a) the dielectric material is an intermetal dielectric and the conductive pathways are metal lines of a metalization layer, (b) the dielectric material is an interlayer dielectric and the conductive pathways include polysilicon gate structures, and (c) the dielectric material is a packaging material and the conductive pathways include a top layer of metalization on the integrated circuit.
The thermally stable polymeric material may be evidenced by a glass transition temperature of at least about 300xc2x0 centigrade. Alternatively or in addition, the thermal stability may be evidenced by the polymeric material retaining at least about 99.5% of its mass when heated to 450xc2x0 centigrade for one hour. Many thermally stable polymeric materials meeting this criteria are fluorocarbon polymers. One particularly preferred fluorocarbon polymer is polyfluoropyreline.
Suitable adhesion promoting polar materials increase the polymeric material""s surface energy and may include, for example, sulfur, phosphorus, nitrogen, or oxygen containing moieties. Such polar material may be integrated within the polymeric material or it may terminate at least some of the polymer chains of the thermally stable polymeric material. In a particularly preferred embodiment, the polymer is polyfluoropyreline and the polar material is thiodifluoromethane integrated with the polyfluoropyreline at a chain terminus.
Preferably, the polar material is localized at the interface between the polymeric material and the one or more conductive pathways. Alternatively, it may be disposed throughout the thermally stable polymeric material.
Another aspect of the invention provides a method of forming a dielectric material for electrically isolating one or more conductive pathways of an electronic circuit. Such method may be characterized as including the following: (a) providing the one or more conductive pathways to a chemical vapor deposition reaction chamber; (b) introducing a polar material precursor into the chemical vapor deposition reaction chamber such that a polar material adheres to the one or more conductive pathways; and (c) introducing a bulk dielectric material monomer into the chemical vapor deposition reaction chamber such that a thermally stable polymeric material deposits on the polar material and forms the dielectric material.
Often, some bulk dielectric material monomer will be introduced with the polar material precursor in (b). In addition, some of the polar material precursor may be introduced with the bulk material dielectric material monomer in (c). In a preferred embodiment, the polar material precursor is di(thiodifluoromethane) and the bulk dielectric material monomer is fluoropyreline.
The di(thiodifluoromethane) may be activated to form thiodifluoromethane (and thereby increase its reactivity) prior to introduction to the chemical vapor deposition reaction chamber in (b). One way to activate the di(thiodifluoromethane) involves heating it in an activation chamber located upstream of the chemical vapor deposition chamber. The fluoropyreline may also be activated in this manner prior to introduction to the chemical vapor deposition reaction chamber in (c).
Spin coating may be employed as an alternative to the chemical vapor deposition process. In this case, the polymer (with polar material) is dissolved in a solvent and provided to a spin coating apparatus. The dielectric layer is then formed as in a conventional spin coating process. In some cases, monomers or other precursors to the dielectric material may be reacted in the solventxe2x80x94possibly during the spin coating processxe2x80x94to form the desired polymeric dielectric.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.